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rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a 12-bit high speed multiplying d/a converter dac312 ? analog devices, inc., 1996 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features differential nonlinearity: 6 1/2 lsb nonlinearity: 0.05% fast settling time: 250 ns high compliance: C5 v to +10 v differential outputs: 0 to 4 ma guaranteed monotonicity: 12 bits low full-scale tempco: 10 ppm/ 8 c circuit interface to ttl, cmos, ecl, pmos/nmos low power consumption: 225 mw industry standard am6012 pinout available in die form pin connections 20-pin hermetic dip (r-suffix), 20-pin plastic dip (p-suffix), 20-pin sol (s-suffix) general description the dac312 series of 12-bit multiplying digital-to-analog con- verters provide high speed with guaranteed performance to 0.012% differential nonlinearity over the full commercial oper- ating temperature range. the dac312 combines a 9-bit master d/a converter with a 3-bit (msbs) segment generator to form an accurate 12-bit d/a converter at low cost. this technique guarantees a very uniform step size (up to 1/2 lsb from the ideal), monotonicity to 12-bits and integral nonlinearity to 0.05% at its differential cur- rent outputs. in order to provide the same performance with a 12-bit r-2r ladder design, an integral nonlinearity over tem- perature of 1/2 lsb (0.012%) would be required. the 250 ns settling time with low glitch energy and low power consumption are achieved by careful attention to the circuit de- sign and stringent process controls. direct interface with all popular logic families is achieved through the logic threshold terminal. functional block diagram high compliance and low drift characteristics (as low as 10 ppm/ c) are also features of the dac312 along with an ex- cellent power supply rejection ratio of .001% fs/% d v. oper- ating over a power supply range of +5/C11 v to 18 v the device consumes 225 mw at the lower supply voltages with an absolute maximum dissipation of 375 mw at the higher supply levels. with their guaranteed specifications, single chip reliability and low cost, the dac312 device makes excellent building blocks for a/d converters, data acquisition systems, video display driv- ers, programmable test equipment and other applications where low power consumption and complete input/output versatility are required.
dac312n dac312g parameter symbol conditions typical typical units reference input slew rate dl/dt 8 8 ma/ m s propagation delay t plh , t phl any bit 25 25 ns settling time t s to 1/2 lsb, all bits switched on 250 250 ns or off. full-scale tc ifs 10 10 ppm/ c rev. c C2C dac312Cspecifications electrical characteristics (@ v s = 6 15 v, i ref = 1.0 ma, 0 8 c t a +70 8 c for dac312e and C40 8 c t a +85 8 c for dac312f, dac312h, unless otherwise noted. output characteristics refer to both i out and i out .) dac312e dac312f dac312h parameter symbol conditions min typ max min typ max min typ max units resolution 12 12 12 bits monotonicity 12 12 12 bits differential nonlinearity dnl deviation from ideal 0.0125 0.0250 0.0250 %fs step size 2 0.5 1 1 lsb nonlinearity inl deviation from ideal 0.05 0.05 0.05 %fs straight line 1 full-scale current i fs v ref = 10 v r 14 = r 15 = 10 k w 2 3.967 3.999 4.031 3.935 3.999 4.063 3.935 3.999 4.063 ma full-scale tempco tci fs 5 20 10 40 80 ppm/ c 0.005 0.002 0.001 0.004 0.008 %fs/ c output voltage compliance v oc dnl specification guaran- teed over compliance range C5 +10 C5 +10 C5 +10 v full-scale symmetry i fss |i fs |C|i fs | 0.4 1 0.4 2 0.4 2 m a zero-scale current i zs 0.10 0.10 0.10 m a settling time t s to 1/2 lsb, all bits switched on or off 1 250 500 250 500 250 500 ns propagation delayCall bits t plh all bits switched 50% point 25 50 25 50 25 50 ns t phl logic swing to 50% point 25 50 25 50 25 50 ns output 1 output resistance r o >10 >10 >10 m w output capacitance c out 20 20 20 pf logic input levels 0 v il v lc = gnd 0.8 0.8 0.8 v levels 1 v ih v lc = gnd 2 2 2 v logic input current i in v in = C5 to +18 v 40 40 40 m a logic input swing v is C5 +18 C5 +18 C5 +18 v reference bias current i 15 0 C0.5 C2 0 C0.5 C2 0 C0.5 C2 m a reference input slew rate dl/dt r 14(eq) = 800 w , c c = 0 pf 1 4 8 48 48 ma/ m s power supply sensitivity pssi fs+ v+ = +13.5 v to +16.5 v, vC = C15 v 0.0005 0.001 0.0005 0.001 0.0005 0.001 %fs/% d v pssi fsC vC = C13.5 v to C16.5 v, v+ = +15 v 0.00025 0.001 0.00025 0.001 0.00025 0.001 %fs/% d v power supply range v+ v out = 0 v 4.5 18 4.5 18 4.5 18 v vC v out = 0 v C18 C10.8 C18 C10.8 C18 C10.8 v power supply current i+ v+ = +5 v, vC = C15 v 3.3 7 3.3 7 3.3 7 ma iC v+ = +15 v, vC = C15 v C13.9 C18 C13.9 C18 C13 9 C18 ma i+ v+ = +5 v, vC = C15 v 3.9 7 3.9 7 3.9 7 ma iC v+ = +15 v, vC = C15 v C13.9 C18 C13.9 C18 C13.9 C18 ma power dissipation p d v+ = +5 v, vC = C15 v 225 305 225 305 225 305 mw v+ = +15 v, vC = C15 v 267 375 267 375 267 375 mw typical electrical characteristics @ 25 8 c; v s = 6 15 v, and i ref = 1.0 ma, unless otherwise noted. output characteristics refer to both i out and i out .
electrical characteristics dac312e dac312f dac312h parameter symbol conditions min typ max min typ max min typ max units logic input levels 0 v il v lc = gnd 0.8 0.8 0.8 v logic input levels 1 v ih v lc = gnd 2 2 2 v logic input current i in v in = C5 v to +18 v 40 40 40 m a logic input swing v is C5 +18 C5 +18 C5 +18 v reference bias current i 15 0 C0.5 C2 0 C0.5 C2 0 C0.5 C2 m a reference input dl/dt r 14(eq) = 800 w 4 8 4 8 4 8 ma/ m s slew rate c c = 0 pf (note 1) v+ = +13.5 v to +16.5 v, 0.0005 0.001 0.0005 0.001 0.0005 0.001 %fs/% d v power supply pssi fs+ vC = C15 v sensitivity pssi fsC vC = C13.5 v to C16.5 v, 0.00025 0.001 0.00025 0.001 0.00025 0.001 %fs/% d v v+ = +15 v power supply v+ 4.5 18 4.5 18 4.5 18 range vC v out = 0 v C18 C10.8 C18 C10.8 C18 C10.8 v i+ 3.3 7 3.3 7 3.3 7 power supply iC v+ = +5 v, vC = C15 v C13.9 C18 C13.9 C18 C13.9 C18 current i+ v+ = +15 v, vC = C15 v 3.9 7 3.9 7 3.9 7 ma iC C13.9 C18 C13.9 C18 C13.9 C18 power v+ = +5 v, vC = C15 v 225 305 225 305 225 305 dissipation p d v+ = +15 v, vC = C15 v 267 375 267 375 267 375 mw notes 1 guaranteed by design. 2 t a = +25 c for dac312h grade only. specifications subject to change without notice. @ v s = 6 15 v, i ref = 1.0 ma, 0 8 c t a 70 8 c for dac312e and C40 8 c t a +85 8 c for dac312f, dac312h, unless otherwise noted. output characteristics refer to both i out and i out . continued C3C rev. c dac312
dac312 C4C rev. c wafer test limits dac312n dac312g parameter symbol conditions limit limit units resolution 12 12 bits min monotonicity 12 12 bits min nonlinearity 0.05 0.05 %fs max output voltage full-scale current +10 +10 v max compliance voc change <1/2 lsb C5 C5 v min full-scale v ref = 10.000 v 4.031 4.063 ma max current r 14 , r 15 = 10.000 k w 3.967 3.935 ma min full-scale symmetry i fss 1 2 m a max zero-scale current i zs 0.1 0.1 m a max differential dnl deviation from 0.012 0.025 %fs max nonlinearity ideal step size 1/2 1 bits (lsb) max logic input levels 0 v il v lc = gnd 0.8 0.8 v max logic input levels 1 v ih v lc = gnd 2 2 v min logic input swing v is +18 +18 v max C5 C5 v min reference bias current i 15 C2 C2 m a max power supply pssi fs+ v+ = +13.5 v to +16.5 v, vC = C15 v 0.001 0.001 sensitivity pssi fsC vC = C13.5 v to C16.5 v, v+ = +15 v 0.001 0.001 %/%max power supply i+ v s = +15 v 7 7 current iC i ref 1.0 ma C18 C18 ma max power v s = +15 v dissipation p d i ref 1.0 ma 375 375 mw max note electrical tests are performed at wafer probe to the limits shown. due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing. @ v s = 6 15 v, i ref = 1.0 ma, t a = 25 8 c, unless otherwise noted. output characteristics refer to both i out and i out . dice characteristics die size 0.141 0.096 inch, 13,536 sq. mils (3.58 2.44 mm, 8.74 sq. mm) 1. b1 (msb) 11. b11 2. b2 12. b12 (lsb) 3. b3 13. v lc /a gnd 4. b4 14. v ref (+) 5. b5 15. v ref (C) 6. b6 16. comp 7. b7 17. vC 8. b8 18. i o 9. b9 19. i o 10. b10 20. v+
dac312 C5C rev. c ordering guide 1 temperature package package model dnl range description option dac312er 2 1/2 lsb 0 c to +70 c cerdip-20 q-20 dac312fr 1 lsb C40 c to +85 c cerdip-20 q-20 dac312br/883 1 lsb C55 c to +125 c cerdip-20 q-20 dac312hp 1 lsb C40 c to +85 c plastic dip-20 n-20 dac312hs 1 lsb C40 c to +85 c sol-20 r-20 notes 1 burn-in is available on commercial and industrial temperature range parts in cerdip, plastic dip, and to-can packages. 2 for devices processed in total compliance to mil-std-883, add/883 after part number. consult factory for 883 data sheet. absolute maximum ratings 1 operating temperature dac312e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 c to +70 c dac312f, dac312h . . . . . . . . . . . . . . . . . . C40 c to +85 c junction temperature . . . . . . . . . . . . . . . . . . . . C65 c to +150 c storage temperature (tj) . . . . . . . . . . . . . . . . . C65 c to +125 c lead temperature (soldering, 60 sec) . . . . . . . . . . . . . . . . 300 c power supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C5 v to +18 v analog current outputs . . . . . . . . . . . . . . . . . . . . C8 v to +12 v reference inputs v 14 , v 15 . . . . . . . . . . . . . . . . . . . . . . . vC to v+ reference input differential voltage (v 14 , v 15 ) . . . . . . . . . . 18 v reference input current (i 14 ) . . . . . . . . . . . . . . . . . . . . . 1.25 ma package type u ja 2 u jc units 20-pin hermetic dip (r) 76 11 c/w 20-pin plastic dip (p) 69 27 c/w 20-pin sol (s) 88 25 c/w notes 1 absolute maximum ratings apply to both dice and packaged parts, unless otherwise noted. 2 q ja is specified for worst case mounting conditions, i.e., q ja is specified for device in socket for cerdip and p-dip packages; q ja is specified for device soldered to printed circuit board for sol package. warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the dac312 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
dac312 C6C rev. c typical performance characteristics output current vs. output voltage (output voltage compliance) power supply current vs. power supply voltage reference amplifier small-signal frequency response reference amplifier common-mode range power supply current vs. temperature reference amplifier large-signal frequency response output compliance vs. temperature true and complementary output operation gain accuracy vs. reference current
dac312 C7C rev. c basic connections negative low impedance output operation accommodating bipolar references basic positive reference operation positive low impedance output operation basic negative reference operation recommended full-scale adjustment circuit pulsed reference operation
dac312 C8C rev. c interfacing with various logic families bipolar offset (true zero) basic connections msb lsb i o i o code format output scale b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 (ma) (ma) v out offset binary; positive full-scale 1 111111111 1 1 3.999 0.000 9.9951 true zero output. positive full-scale Clsb 1 111111111 1 0 3.998 0.001 9.9902 +lsb 1 000000000 0 1 2.001 1.998 0.0049 zero-scale 1 000000000 0 0 2.000 1.999 0.000 Clsb 0 111111111 1 1 1.999 2.000 C0.0049 negative full-scale +lsb 0 000000000 0 1 0.001 3.998 C9.9951 negative full-scale 0 000000000 0 0 0.000 3.999 C10.000 2s complement; positive full-scale 0 111111111 1 1 3.999 0.000 9.9951 true zero output positive full-scale Clsb 0 111111111 1 0 3.998 0.001 9.9902 msb complemented +1 lsb 0 000000000 0 1 2.001 1.998 0.0049 (need inverter at b1). zero-scale 0 000000000 0 0 2.000 1.999 0.000 C1 lsb 1 111111111 1 1 1.999 2.000 C0.0049 negative full-scale +lsb 1 000000000 0 1 0.001 3.998 C9.9951 negative full-scale 1 000000000 0 0 0.000 3.999 C10.000
dac312 C9C rev. c basic connections basic unipolar operation symmetrical offset operation msb lsb i o i o code format output scale b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 (ma) (ma) v out straight binary; positive full-scale 1111111111 1 1 3.999 0.000 9.9976 unipolar with true positive full-scale Clsb 1111111111 1 0 3.998 0.001 9.9951 input code, true lsb 0000000000 0 1 0.001 3.998 0.0024 zero output. zero-scale 0000000000 0 0 0.000 3.999 0.0000 complementary binary; positive full-scale 0000000000 0 0 0.000 3.999 9.9976 unipolar with positive full-scale Clsb 0000000000 0 1 0.001 3.998 9.9951 complementary input lsb 1111111111 1 0 3.998 0.001 0.0024 code, true zero output. zero-scale 1111111111 1 1 3.999 0.000 0.0000 msb lsb i o i o code format output scale b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 (ma) (ma) v out straight offset binary; positive full-scale 1 1 1 1 1 1 1 1 1 1 1 1 3.999 0.00 9.9976 symmetrical about zero, positive full-scale Clsb 1 1 1 1 1 1 1 1 1 1 1 0 3.998 0.001 9.9927 no true zero output. (+) zero-scale 1 0 0 0 0 0 0 0 0 0 0 0 2.000 1.999 0.0024 (C) zero-scale 0 1 1 1 1 1 1 1 1 1 1 1 1.999 2.000 C0.0024 negative full-scale Clsb 0 0 0 0 0 0 0 0 0 0 0 1 0.001 3.998 C9.9927 negative full-scale 0 0 0 0 0 0 0 0 0 0 0 0 0.000 3.999 C9.9976 1s complement; positive full-scale 0 1 1 1 1 1 1 1 1 1 1 1 3.999 0.000 9.9976 symmetrical about zero, positive full-scale Clsb 0 1 1 1 1 1 1 1 1 1 1 0 3.998 0.001 9.9927 no true zero output. (+) zero-scale 0 0 0 0 0 0 0 0 0 0 0 0 2.000 1.999 0.0024 msb complemented (C) zero-scale 1 1 1 1 1 1 1 1 1 1 1 1 1.999 2.000 C0.0024 (need inverter at b1). negative full-scale Clsb 1 0 0 0 0 0 0 0 0 0 0 1 0.001 3.998 C9.9927 negative full-scale 1 0 0 0 0 0 0 0 0 0 0 0 0.000 3.999 C9.9976
dac312 C10C rev. c applications information reference amplifier setup the dac312 is a multiplying d/a converter in which the out- put current is the product of a digital number and the input ref- erence current. the reference current may be fixed or may vary from nearly zero to +1.0 ma. the full range output current is a linear function of the reference current and is given by: i fr = 4095 4096 4 (i ref ) = 3.999 i ref , where i ref = i 14 in positive reference applications, an external positive reference voltage forces current through r14 into the v ref(+) terminal (pin 14) of the reference amplifier. alternatively, a negative ref- erence may be applied to v ref(C) at pin 15. reference current flows from ground through r14 into v ref(+) as in the positive reference case. this negative reference connection has the ad- vantage of a very high impedance presented at pin 15. the volt- age at pin 14 is equal to and tracks the voltage at pin 15 due to the high gain of the internal reference amplifier. r15 (nominally equal to r14) is used to cancel bias current errors. bipolar references may be accommodated by offsetting v ref or pin 15. the negative common-mode range of the reference am- plifier is given by: v cm C = vC plus (i ref 3 k w ) plus 1.23 v. the positive common-mode range is v+ less 1.8 v. when a dc reference is used, a reference bypass capacitor is rec- ommended. a 5.0 v ttl logic supply is not recommended as a reference. if a regulated power supply is used as a reference, r14 should be split into two resistors with the junction bypassed to ground with a 0.1 m f capacitor. for most applications the tight relationship between i ref and i fs will eliminate the need for trimming i ref . if required, full scale trimming may be accomplished by adjusting the value of r14, or by using a potentiometer for r14. an improved method of full-scale trimming which eliminates potentiometer t.c. effects is shown in the recommended full-scale adjustment circuit. the reference amplifier must be compensated by using a capaci- tor from pin 16 to vC. for fixed reference operation, a 0.01 m f capacitor is recommended. for variable reference applications, see section entitled reference amplifier compensation for multiplying applications. multiplying operation the dac312 provides excellent multiplying performance with an extremely linear relationship between i fs and i ref over a range of 1 ma to 1 m a. monotonic operation is maintained over a typical range of i ref from 100 m a to 1.0 ma. although some degradation of gain accuracy will be realized at reduced values of i ref . (see gain accuracy vs. reference current). reference amplifier compensation for multiplying applications ac reference applications will require the reference amplifier to be compensated using a capacitor from pin 16 to vC. the value of this capacitor depends on the impedance presented to pin 14 for r14 values of 1.0 w , 2.5 w and 5.0 k w , minimum values of c c are 5 pf, 10 pf, and 25 pf. larger values of r14 require proportionately increased values of c c for proper phase margin. for fastest response to a pulse, low values of r14 enabling small c c values should be used. if pin 14 is driven by a high imped- ance such as a transistor current source, none of the above val- ues will suffice and the amplifier must be heavily compensated which will decrease overall bandwidth and slew rate. for r14 = 1 k w and c c = 5 pf, the reference amplifier slews at 4 ma/ m s enabling a transition from i ref = 0 to i ref = 1 ma in 250 ns. operation with pulse inputs to the reference amplifier may be accommodated by an alternate compensation scheme. this technique provides lowest full-scale transition times. an internal clamp allows quick recovery of the reference amplifier from a cutoff (i ref = 0) condition. full-scale transition (0 ma to 1 ma) occurs in 62.5 ns when the equivalent impedance at pin 14 is 800 w and c c = 0. this yields a reference slew rate of 8 ma/ m s which is relatively independent of r in and v in values. logic inputs the dac312 design incorporates a unique logic input circuit which enables direct interface to all popular logic families and provides maximum noise immunity. this feature is made pos- sible by the large input swing capability, 40 m a logic input cur- rent, and completely adjustable logic threshold voltage. for vC = C15 v, the logic inputs may swing between C5 v and +10 v. this enables direct interface with +15 v cmos logic, even when the dac312 is powered from a +5 v supply. minimum input logic swing and minimum logic threshold voltage are given by: vC plus (i ref 3 k w ) plus 1.8 v. the logic threshold may be adjusted over a wide range by placing an appropriate voltage at the logic threshold control pin (pin 13, v lc ). the appropriate graph shows the relationship between v lc and v th over the temperature range, with v th nominally 1.4 above v lc . for ttl interface, simply ground pin 13. when interfacing ecl, an i ref 1 ma is recommended. for interfacing other logic families, see block titled interfacing with various logic fami- lies. for general setup of the logic control circuit, it should be noted that pin 13 will sink 7 ma typical; external circuitry should be designed to accommodate this current.
dac312 C11C rev. c analog output currents both true and complemented output sink currents are provided where i o + i o = i fr . current appears at the true output when a 1 is applied to each logic input. as the binary count increases, the sink current at pin 18 increases proportionally, in the fash- ion of a positive logic d/a converter. when a 0 is applied to any input bit, that current is turned off at pin 18 and turned on at pin 19. a decreasing logic count increases i o as in a negative or inverted logic d/a converter. both outputs may be used si- multaneously. if one of the outputs is not required it must still be connected to ground or to a point capable of sourcing i fr ; do not leave an unused output pin open. both outputs have an extremely wide voltage compliance en- abling fast direct current-to-voltage conversion through a resis- tor tied to ground or other voltage source. positive compliance is 25 v above vC and is independent of the positive supply. negative compliance is +10 v above vC. the dual outputs enable double the usual peak-to-peak load swing when driving loads in quasi-differential fashion. this fea- ture is especially useful in cable driving, crt deflection and in other balanced applications such as driving center-tapped coils and transformers. power supplies the dac312 operates over a wide range of power supply volt- ages from a total supply of 20 v to 36 v. when operating with vC supplies of C10 v or less, i ref 1 ma is recommended. low reference current operation decreases power consumption and increases negative compliance, reference amplifier negative common-mode range, negative logic input range, and negative logic threshold range; consult the various figures for guidance. for example, operation at C9 v with i ref = 1 ma is not recom- mended because negative output compliance would be reduced to near zero. operation from lower supplies is possible, however at least 8 v total must be applied to insure turn-on of the inter- nal bias network. symmetrical supplies are not required, as the dac312 is quite insensitive to variations in supply voltage. battery operation is feasible as no ground connection is required; however, an artifi- cial ground may be used to insure logic swings, etc. remain be- tween acceptable limits. temperature performance the nonlinearity and monotonicity specifications of the dac312 are guaranteed to apply over the entire rated operating temperature range. full-scale output current drift is tight, typi- cally 10 ppm/ c, with zero-scale output current and drift es- sentially negligible compared to 1/2 lsb. the temperature coefficient of the reference resistor r14 should match and track that of the output resistor for minimum overall full-scale drift. settling times of the dac312 decrease approxi- mately 10% at C55 c; at +125 c an increase of about 15% is typical. settling time the dac312 is capable of extremely fast settling times; typi- cally 250 ns at i ref = 1.0 ma. judicious circuit design and care- ful board layout must be employed to obtain full performance potential during testing and application. the logic switch design enables propagation delays of only 25 ns for each of the 12 bits. settling time to within 1/2 lsb of the lsb is therefore 25 ns, with each progressively larger bit taking successively longer. the msb settles in 250 ns, thus determining the overall settling time of 250 ns. settling to 10-bit accuracy requires about 90 ns to 130 ns. the output capacitance of the dac312 including the package is approximately 20 pf; therefore, the output rc time constant dominates settling time if r l > 500 w . settling time and propagation delay are relatively insensitive to logic input amplitude and rise and fall times, due to the high gain of the logic switches. settling time also remains essentially constant for i ref values down to 0.5 ma, with gradual increases for lower i ref values lies in the ability to attain a given output level with lower load resistors, thus reducing the output rc time constant. measurement of the settling time requires the ability to accu- rately resolve 1/2 lsb of current, which is 500 na for 4 ma fsr. in order to assure the measurement is of the actual settling time and not the rc time of the output network, the resistive termination on the output of the dac must be 500 w or less. this does, however, place certain limitations on the testing ap- paratus. at i ref values of less than 0.5 ma, it is difficult to pre- vent rc damping of the output and maintain adequate sensitivity. because the dac312 has 8 equal current sources for the 3 most significant bits, the major carry occurs at the code change of 000111111111 to 111000000000. the worst case set- tling time occurs at the zero to full-scale transition and it re- quires 9.2 time constants for the dac output to settle to within 1/2 lsb (0.0125%) of its final value. the dac312 switching transients or glitches are on the order of 500 mv-ns. this is most evident when switching through the major carry and may be further reduced by adding small capaci- tive loads at the output with a minor sacrifice in transition speeds. fastest operation can be obtained by using short leads, minimiz- ing output capacitance and load resistor values, and by adequate bypassing at the supply, reference, and v lc terminals. supplies do not require large electrolytic bypass capacitors as the supply current drain is independent of input logic states; 0.1 m f capaci- tors at the supply pins provide full transient protection.
dac312 C12C rev. c one of the characteristics of an r-2r dac in standard form is that any transition which causes a zero lsb change (i.e., the same output for two different codes) will exhibit the same out- put each time that transition occurs. the same holds true for transitions causing a 2 lsb change. these two problem transi- tions are allowable for the standard definition of monotonicity and also allow the device to be specified very tightly for inl. the major problem arising from this error type is in a/d con- verter implementations. inputs producing the same output are now represented by ambiguous output codes for an identical in- put. also, 2 lsb gaps can cause large errors at those input lev- els (assuming 1/2 lsb quantizing levels). it can be seen from the two figures that the dnl specified d/a converter will yield much finer grained data than the inl specified part, thus im- proving the ability of the a/d to resolve changes in the analog input. differential linearity comparison d/a converter with 1/2 lsb inl, 1 lsb dnl video deflection by dacs enlarged positional outputs d/a converter with 2 lsb inl, 1/2 lsb dnl video deflection by dacs enlarged positional outputs differential vs. integral nonlinearity integral nonlinearity, for the purposes of the discussion, refers to the straightnessof the line drawn through the individual re- sponse points of a data converter. differential nonlinearity, on the other hand, refers to the deviation of the spacing of the adja- cent points from a 1 lsb ideal spacing. both may be expressed as either a percentage of full-scale output or as fractional lsbs or both. the following figures define the manner in which these parameters are specified. the left figure shows a portion of the transfer curve of a dac with 1/2 lsb inl and the (implied) dnl spec of 1 lsb. below this is a graphic representation of the way this would appear on a crt, for example, if the d/a converter output were to be applied to the y input of a crt as shown in the application schematic titled crt display drive. on the right is a portion of the transfer curve of a dac speci- fied for 2 lsb inl with 1/2 lsb dnl specified and the graphic display below it.
dac312 C13C rev. c description of operation the dac312 is divided into two major sections, an 8 segment generator and a 9-bit master/slave d/a converter. in operation the device performs as follows (see simplified schematic). the three most significant bits (msbs) are inputs to a 3-to-8 line decoder. the selected resistor (r5 in the figure) is con- nected to the master/slave 9-bit d/a converter. all lower order resistors (r1 through r4) are summed into the i o line, while all higher order resistors (r6 through r8) are summed into the i o line. the r5 current supplies 512 steps of current (0 ma to 0.499 ma for a 1 ma reference current) which are also summed into the i o or i o lines depending on the bits selected. in the fig- ure, the code selected is: 100 110000000. therefore, 2 ma (4 0.5 ma/segment) +0.375 ma (from master/slave d/a converter) are summed into i o giving an i o of 2.375 ma. i o has a current of 1.625 ma with this code. as the three msbs are increment- ed, each successively higher code adds 0.5 ma to i o and sub- tracts 0.5 ma from i o , with the selected resistor feeding its current to the master/slave d/a converter; thus each increment of the 3 msbs allows the current in the 9-bit d/a converter to be added to a pedestal consisting of the sum of all lower order currents from the segment generator. this configuration guar- antees monotonicity. expanded transfer characteristic segment (001 010 011) simplified schematic
000000000 printed in u.s.a. C14C 12-bit fast a/d converter outline dimensions dimension shown in inches and (mm). 20-lead plastic dip (n-20) 20-lead cerdip (q-20) 20-lead wide body sol (r-20)
package/price information for detailed packaging information, please select the datasheets button. 12-bit high speed multiplying d/a converter ?model? status package description pin count temperature range price* (100-499) ?dac312br? ?production? ?cerdip glass seal? ?20? ?military? ?$29.65? ?dac312br/883c? ?production? ?cerdip glass seal? ?20? ?military? ?$34.60? ?dac312er? ?production? ?cerdip glass seal? ?20? ?industrial? ?$19.75? ?dac312fr? ?production? ?cerdip glass seal? ?20? ?industrial? ?$9.85? ?DAC312GBC? ?production? ?chips/die sales? - ?tbd? ?$4.00? ?dac312hp? ?production? ?plastic/epoxy dip? ?20? ?commercial? ?$4.50? ?dac312hs? ?production? ?std s.o. pkg (soic)? ?20? ?commercial? ?$4.50? * this price is provided for budgetary purposes as recommended list price in u.s. dollars per unit the stated volume. pricing displayed for evaluation boards and kits is based on 1-piece pricing. view pricing and availability (currently available to north american customers) for further information. analog products -- dac312 file:///f|/cpl_new_images/dac312.html [7/18/2001 5:37:32 pm]

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